Instruction data of a processor is read from an SRAM at a level in a memory hierarchy that is closest to an arithmetic pipeline. With the objective of preventing the execution of an illegal instruction by things such as a soft error occurred in the SRAM, syndrome bits are added to implement an Error Correcting Code (ECC) circuit that detects and corrects the occurrence of an error in the data.
Meanwhile, an arithmetic path length of a circuit for the generation of FCC syndrome bits and for detection and correction with its result tends to be longer than an operation cycle of the pipeline, and the operation frequency of an entire block is limited. Hence, it is conceivable that the ECC circuit is divided into stages. However, one or more cycles are required upon error correction, and corrected data is written back into the SRAM to prevent the accumulation of errors. Accordingly, a situation where instructions cannot be continuously provided into the pipeline arises, which results in reduction in an instruction execution throughput.